Each SSD’s fundamental building block is the floating gate transistor, consisting of a source, drain, silicon insulator, a floating gate, and a control gate
Research Details: GitHub Link
Each NAND Flash cell has a limited P/E cycle. So this research aims to improve lifespan of SSDs by predicting Update Period. But If we predict the Update Period by ML, It causes latency problem. To resolve latency problem, we use FPGA as an accelerator for Update Period Prediction Model.
Research Details: GitHub Link
Each SSD’s fundamental building block is the floating gate transistor, consisting of a source, drain, silicon insulator, a floating gate, and a control gate
Research Details: GitHub Link
Understanding the intricacies of Flash SSD technology can be challenging for students without a solid foundation.
GitHub Link